1. Field of the Invention
The present invention relates to a sense amplifier for a programmable read only memory such as an erasable programmable read only memory (EPROM).
2. Description of the Related Art
In general, a conventional EPROM includes a sense amplifier having a p-channel load transistor, an n-channel drive transistor, a sense output terminal, a memory cell array having a plurality of memory cell transistors, and bit lines and word lines. When a field effect transistor having a stacked-gate structure is used as a memory cell of an EPROM, the transistor injects and stores hot electrons, generated by an avalanche breakdown occurring at the drain terminal, into a floating gate during a program operation, so that the changes in threshold voltage Vth of the transistor are utilized.
In the EPROM which uses the field effect transistor having a stacked-gate structure, since an electric charge is stored in the floating gate of the program, i.e., written, memory cell transistor as described above, it is difficult to pass a drain current, i.e., a cell current, therethrough. Therefore, when data is read in such a case, the potential of the sense output is HIGH level "1". Conversely, since an electric charge is not stored in the floating gate of the non-programmed memory cell transistor, it is easy to flow a cell current therethrough. Therefore, when data is read in such a case, the potential of the sense output is LOW level "0".
In order to program, i.e., write in, the EPROM which uses the field effect transistor having the stacked-gate structure, a power supply voltage V.sub.pp for programming is applied to the memory. The power supply voltage V.sub.pp for programming is, for example, 12 V, which is a higher value than a power supply voltage V.sub.cc for reading (for example, 5 V). In this case, a voltage of about 10 V is applied between the drain and the source of the cell transistor, and a voltage of about 12 V is applied to a control gate electrode at the surface. Note that, during a verify read operation, the power supply voltage V.sub.pp for programming is applied to the memory, and the power supply voltage V.sub.cc for reading is applied to the memory cell transistor and other necessary sections by a suitable switch circuit, but during a regular read operation, only the power supply voltage V.sub.cc for reading is applied to the memory.
In the above-mentioned EPROM, the completion of a write operation is verified by detecting whether the sense current exceeds the reference value. That is, the voltage V.sub.pp for programming is applied to carry out the write operation as described above. The power supply voltage V.sub.cc for reading is switched and applied to carry out the verify reading operation while the power supply voltage V.sub.pp for programming is still applied. If a cell current exceeding the reference value does not flow in the memory cell transistor, the write operation is determined to be completed.
During the above verify reading, the power supply voltage V.sub.pp for programming of, for example, 12 V, and the power supply voltage V.sub.cc for reading of, for example, 5 V, are applied to the memory, and the power supply voltage V.sub.cc for reading is applied to the memory cell transistor 51. Assuming that the power supply voltage V.sub.cc for reading is, for example, 5 V, a voltage of 5 V is applied to the control gate electrode at the surface of the memory cell transistor, and a voltage of about 1 V is applied between the drain and the source.
The reference value of the cell current for carrying out a discrimination between "1" and "0" in the case of the verify reading is the same as that in the case of the regular reading.
In the case of programming the above EPROM, when the reference value of the cell current for discriminating whether the write operation is completed is set, for example, as 10 .mu.A, the write operation is determined to be completed if the cell current is, for example, 9 .mu.A, during the verify reading.
However, after long-term use of the memory, often the electric charges will leak from the floating gate of the memory cell transistor. As a result, the cell current increases by an amount of, for example, 1 .mu.A.
Under such a condition, when the regular read operation is performed and a cell current of 10 .mu.A flows, it is recognized that the potential of the sense output is LOW level "0", although the potential of the sense output should be recognized as being HIGH level "1". Hence, the discrimination between "1" and "0" in the regular reading becomes incorrect. Therefore, the operation of the EPROM can become defective.